Independent researcher Eileen Yoon published a detailed reverse-engineering of Apple's Neural Engine, the M1 chip's dedicated machine learning accelerator, revisiting a project she had abandoned three years earlier, according to her blog post.
Yoon mapped the ANE's compute, memory and execution model in full: 16 cores with 256 FP16 multiply-accumulate lanes each, for 2,048 parallel lanes total, running compiled models as serialized "task descriptors" rather than a conventional instruction set. The chip has no fixed operation for convolutions versus attention, she wrote; the same dot-product hardware is reused for both, with specialization coming from how the surrounding dataflow is arranged for predictable reuse patterns.
A roofline analysis in the post found the ANE needs 162 operations per byte of DRAM traffic to keep its compute fully fed, while its kernel and tile DMA engines measured only 38 and 59 gigabytes per second, respectively, and run serially rather than in parallel, Yoon wrote.
The ANE's design bet was on the kind of static, highly reused kernels that convolutional networks need, which is not what transformer workloads with dynamic kernel access provide. That mismatch is a concrete reason Apple's M5 folds ANE cores into the GPU instead of scaling the ANE further, and it is useful data for any team deciding whether to target Apple's neural accelerator or fall back to the GPU for on-device transformer inference.