OpenAI used its own AI models throughout the design of Jalapeno, its first AI accelerator chip, cutting the concept-to-silicon timeline to under 20 months, IEEE Spectrum reported based on interviews with OpenAI's hardware team. The time from first RTL code to tape-out fell to nine months.
Richard Ho, OpenAI's vice president of hardware, said the models are "giving superpowers to our engineers." The team used Google's XLS toolchain with languages like DSLX and C++ for high-level synthesis because, as OpenAI technical staff member Chris Leary put it, the process "looks like software," making it a natural fit for LLM assistance.
On one software optimization benchmark from DeepSeek, model-assisted tuning took performance from 0.31% to 88.94% of a target score in roughly 40 hours, according to Spectrum. AI-guided physical design work also cut the area of the chip's matrix multiplication units by 10%. OpenAI said the project drew on a progression of internal models running from o3 through precursors of GPT-6 Astra.
Jalapeno delivers 13.4 petaflops of 4-bit compute with 232 gigabytes of HBM4 memory at 15.4 terabytes per second of bandwidth, and OpenAI says it cuts end-to-end latency by up to 3.6 times versus Nvidia's GB300 at lower power, according to figures the company gave Spectrum.
Chip design has some of the longest feedback loops in engineering: a bad choice doesn't show up until silicon comes back from the fab months later. If LLMs are actually shortening that concept-to-tape-out cycle by a meaningful amount, it is one of the more concrete tests of the claim that AI makes engineers faster, because the output, a working chip, is unusually hard to fake.